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Features
* * * * * * * * * *
Serial Peripheral Interface (SPI) Compatible Supports SPI Modes 0 (0,0) and 3 (1,1) Data Sheet Describes Mode 0 Operation Low-voltage Operation - 1.8 (VCC = 1.8V to 5.5V) 20 MHz Clock Rate (4.5 - 5.5V) 128-byte Page Mode and Byte Write Operation Supported Block Write Protection - Protect 1/4, 1/2, or Entire Array Write Protect (WP) Pin and Write Disable Instructions for Both Hardware and Software Data Protection Self-timed Write Cycle (5 ms Max) High-reliability - Endurance: 1 Million Write Cycles - Data Retention: >40 Years Lead-free/Halogen-free Devices 8-lead JEDEC SOIC, 8-lead TSSOP and 8-lead SAP Packages Die Sales: Wafer Form, Waffle Pack, and Bumped Die
SPI Serial EEPROM
512K (65,536 x 8)
* * *
AT25512
Description
The AT25512 provides 524,288 bits of serial electrically-erasable programmable read only memory (EEPROM) organized as 65,536 words of 8 bits each. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. The devices are available in space saving 8-lead JEDEC SOIC, 8-lead TSSOP and 8-lead SAP packages. In addition, the entire family is available in 1.8V (1.8V to 5.5V) versions. The AT25512 is enabled through the Chip Select pin (CS) and accessed via a 3-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). All programming cycles are completely self-timed, and no separate Erase cycle is required before Write.
Table 0-1.
Pin Name CS SCK SI SO GND VCC WP HOLD NC
Pin Configurations
Function Chip Select Serial Data Clock Serial Data Input Serial Data Output Ground Power Supply Write Protect Suspends Serial Input No Connect
CS SO WP GND CS SO WP GND 1 2 3 4 8 7 6 5 VCC HOLD SCK SI
8-lead SOIC
8-lead TSSOP
1 2 3 4 8 7 6 5 VCC HOLD SCK SI VCC HOLD SCK SI
8-lead SAP
8 7 6 5 1 2 3 4 CS SO WP GND
Bottom View
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Block Write protection is enabled by programming the status register with top 1/4, top 1/2 or entire array of write protection. Separate Program Enable and Program Disable instructions are provided for additional data protection. Hardware data protection is provided via the WP pin to protect against inadvertent write attempts to the status register. The HOLD pin may be used to suspend any serial communication without resetting the serial sequence.
1. Absolute Maximum Ratings*
Operating Temperature.................................-55 C to +125 C Storage Temperature ....................................-65 C to +150 C Voltage on Any Pin with Respect to Ground .................................... -1.0V to +7.0V Maximum Operating Voltage ............................................ 4.3V DC Output Current........................................................ 5.0 mA *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Figure 1-1.
Block Diagram
65536x 8
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AT25512
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AT25512
Table 1-1. Pin Capacitance(1) Applicable over recommended operating range from TA = 25 C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted)
Symbol COUT CIN Note: Test Conditions Output Capacitance (SO) Input Capacitance (CS, SCK, SI, WP, HOLD) 1. This parameter is characterized and is not 100% tested. Max 8 6 Units pF pF Conditions VOUT = 0V VIN = 0V
Table 1-2. DC Characteristics Applicable over recommended operating range from TAI = -40C to +85C, VCC = +1.8V to +5.5V, VCC = +1.8V to +5.5V(unless otherwise noted)
Symbol VCC1 VCC2 VCC3 ICC1 ICC2 ICC3 ISB1 ISB2 ISB3 IIL IOL VIL
(1) (1)
Parameter Supply Voltage Supply Voltage Supply Voltage Supply Current Supply Current Supply Current Standby Current Standby Current Standby Current Input Leakage Output Leakage Input Low-voltage Input High-voltage Output Low-voltage Output High-voltage Output Low-voltage Output High-voltage
Test Condition
Min 1.8 2.7 4.5
Typ
Max 5.5 5.5 5.5
Units V V V mA mA mA A A A A A V V V V
VCC = 5.0V at 20 MHz, SO = Open, Read VCC = 5.0V at 10 MHz, SO = Open, Read, Write VCC = 5.0V at 1 MHz, SO = Open, Read, Write VCC = 1.8V, CS = VCC VCC = 2.7V, CS = VCC VCC = 5.0V, CS = VCC VIN = 0V to VCC VIN = 0V to VCC, TAC = 0 C to 70 C -3.0 -3.0 -1.0 VCC x 0.7 3.6 VCC 5.5V 1.8V VCC 3.6V IOL = 3.0 mA IOH = - mA 1.6 IOL = 0.15 mA IOH = - 100 A VCC -0.2 VCC -0.8
9.0 5.0 2.2 0.2 0.5 2.0
10.0 7.0 3.5 3.0 3.0 5.0 3.0 3.0 VCC x 0.3 VCC + 0.5 0.4
VIH
VOL1 VOH1 VOL2 VOH2 Note:
0.2
V V
1. VIL min and VIH max are reference only and are not tested.
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Table 1-3. AC Characteristics Applicable over recommended operating range from TAI = -40 C to + 85 C, VCC = As Specified, CL = 1 TTL Gate and 30 pF (unless otherwise noted)
Symbol fSCK Parameter SCK Clock Frequency Voltage 4.5-5.5 2.7-5.5 1.8-5.5 4.5-5.5 2.7-5.5 1.8-5.5 4.5-5.5 2.7-5.5 1.8-5.5 4.5-5.5 2.7-5.5 1.8-5.5 4.5-5.5 2.7-5.5 1.8-5.5 4.5-5.5 2.7-5.5 1.8-5.5 4.5-5.5 2.7-5.5 1.8-5.5 4.5-5.5 2.7-5.5 1.8-5.5 4.5-5.5 2.7-5.5 1.8-5.5 4.5-5.5 2.7-5.5 1.8-5.5 4.5-5.5 2.7-5.5 1.8-5.5 4.5-5.5 2.7-5.5 1.8-5.5 4.5-5.5 2.7-5.5 1.8-5.5 4.5-5.5 2.7-5.5 1.8-5.5 4.5-5.5 2.7-5.5 1.8-5.5 20 40 80 20 40 80 100 100 200 100 100 200 100 100 200 5 10 20 5 10 20 5 10 20 5 10 20 0 0 0 0 0 0 0 0 0 25 50 100 20 40 80 Min 0 0 0 Max 20 10 5 2 2 2 2 2 2 Units MHz
tRI
Input Rise Time
s
tFI
Input Fall Time
s
tWH
SCK High Time
ns
tWL
SCK Low Time
ns
tCS
CS High Time
ns
tCSS
CS Setup Time
ns
tCSH
CS Hold Time
ns
tSU
Data In Setup Time
ns
tH
Data In Hold Time
ns
tHD
Hold Setup Time
ns
tCD
Hold Hold Time
ns
tV
Output Valid
ns
tHO
Output Hold Time
ns
tLZ
Hold to Output Low Z
ns
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AT25512
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AT25512
Table 1-3. AC Characteristics (Continued) Applicable over recommended operating range from TAI = -40 C to + 85 C, VCC = As Specified, CL = 1 TTL Gate and 30 pF (unless otherwise noted)
Symbol tHZ Parameter Hold to Output High Z Voltage 4.5-5.5 2.7-5.5 1.8-5.5 4.5-5.5 2.7-5.5 1.8-5.5 4.5-5.5 2.7-5.5 1.8-5.5 1M Min Max 25 50 100 25 50 100 5 5 5 Units ns
tDIS
Output Disable Time
ns
tWC Endurance(1) Notes:
Write Cycle Time 5.0V, 25 C, Page Mode
ms Write Cycles
1. This parameter is characterized and is not 100% tested. Contact Atmel for further information.
2. Serial Interface Description
MASTER: The device that generates the serial clock. SLAVE: Because the serial clock pin (SCK) is always an input, the AT25512 always operates as a slave. TRANSMITTER/RECEIVER: The AT25512 has separate pins designated for data transmission (SO) and reception (SI). MSB: The Most Significant Bit (MSB) is the first bit transmitted and received.
SERIAL OP-CODE: After the device is selected with CS going low, the first byte will be received. This byte contains the op-code that defines the operations to be performed. INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the AT25512, and the serial output pin (SO) will remain in a high impedance state until the falling edge of CS is detected again. This will reinitialize the serial communication. CHIP SELECT: The AT25512 is selected when the CS pin is low. When the device is not selected, data will not be accepted via the SI pin, and the serial output pin (SO) will remain in a high impedance state. HOLD: The HOLD pin is used in conjunction with the CS pin to select the AT25512. When the device is selected and a serial sequence is underway, HOLD can be used to pause the serial communication with the master device without resetting the serial sequence. To pause, the HOLD pin must be brought low while the SCK pin is low. To resume serial communication, the HOLD pin is brought high while the SCK pin is low (SCK may still toggle during HOLD). Inputs to the SI pin will be ignored while the SO pin is in the high impedance state. WRITE PROTECT: The write protect pin (WP) will allow normal read/write operations when held high. When the WP pin is brought low and WPEN bit is "1", all write operations to the status register are inhibited. WP going low while CS is still low will interrupt a write to the status register. If the internal write cycle has already been initiated, WP going low will have no effect on any write operation to the status register. The WP pin function is blocked when the WPEN bit in the status register is "0". This will allow the user to install the AT25512 in a system with the WP pin tied to
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ground and still be able to write to the status register. All WP pin functions are enabled when the WPEN bit is set to "1". Figure 2-1. SPI Serial Interface
AT25512
3. Functional Description
The AT25512 is designed to interface directly with the synchronous serial peripheral interface (SPI) of the 6800 type series of microcontrollers. The AT25512 utilizes an 8-bit instruction register. The list of instructions and their operation codes are contained in see Table 4-3. All instructions, addresses, and data are transferred with the MSB first and start with a high-to-low CS transition.
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AT25512
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AT25512
Table 3-1.
Instruction Set for the AT25512
Instruction Format 0000 X110 0000 X100 0000 X101 0000 X001 0000 X011 0000 X010 Operation Set Write Enable Latch Reset Write Enable Latch Read Status Register Write Status Register Read Data from Memory Array Write Data to Memory Array
Instruction Name WREN WRDI RDSR WRSR READ WRITE
WRITE ENABLE (WREN): The device will power-up in the write disable state when VCC is applied. All programming instructions must therefore be preceded by a Write Enable instruction. WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the Write Disable instruction disables all programming modes. The WRDI instruction is independent of the status of the WP pin. READ STATUS REGISTER (RDSR): The Read Status Register instruction provides access to the status register. The Ready/Busy and Write Enable status of the device can be determined by the RDSR instruction. Similarly, the Block Write Protection bits indicate the extent of protection employed. These bits are set by using the WRSR instruction. Table 3-2.
Bit 7 WPEN
Status Register Format
Bit 6 X Bit 5 X Bit 4 X Bit 3 BP1 Bit 2 BP0 Bit 1 WEN Bit 0 RDY
Table 3-3.
Bit
Read Status Register Bit Definition
Definition
Bit 0 (RDY) Bit 1 (WEN) Bit 2 (BP0) Bit 3 (BP1)
Bit 0 = "0" (RDY) indicates the device is ready. Bit 0 = "1" indicates the write cycle is in progress. Bit 1 = 0 indicates the device is not write enabled. Bit 1 = "1" indicates the device is write enabled. See Table 3-4 on page 8. See Table 3-4 on page 8.
Bits 4 -6 are 0s when device is not in an internal write cycle. Bit 7 (WPEN) See Table 3-5 on page 8. Bits 0 -7 are "1"s during an internal write cycle.
WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to select one of four levels of protection. The AT25512 is divided into four array segments. Top quarter (1/4), top half (1/2), or all of the memory segments can be protected. Any of the data within any selected segment will therefore be read only. The block write protection levels and corresponding status register control bits are shown in Table 3-4.
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The three bits, BP0, BP1, and WPEN are nonvolatile cells that have the same properties and functions as the regular memory cells (e.g. WREN, tWC, RDSR). Table 3-4. Block Write Protect Bits
Status Register Bits Level 0 1(1/4) 2(1/2) 3(All) BP1 0 0 1 1 BP0 0 1 0 1 Array Addresses Protected AT25512 None C000 - FFFF 8000 - FFFF 0000 - FFFF
The WRSR instruction also allows the user to enable or disable the write protect (WP) pin through the use of the write protect enable (WPEN) bit. Hardware write protection is enabled when the WP pin is low and the WPEN bit is "1". Hardware write protection is disabled when either the WP pin is high or the WPEN bit is "0". When the device is hardware write protected, writes to the Status Register, including the Block Protect bits and the WPEN bit, and the blockprotected sections in the memory array are disabled. Writes are only allowed to sections of the memory which are not block-protected. NOTE: When the WPEN bit is hardware write protected, it cannot be changed back to "0", as long as the WP pin is held low. Table 3-5.
WPEN 0 0 1 1 X X
WPEN Operation
WP X X Low Low High High WEN 0 1 0 1 0 1 Protected Blocks Protected Protected Protected Protected Protected Protected Unprotected Blocks Protected Writable Protected Writable Protected Writable Status Register Protected Writable Protected Protected Protected Writable
READ SEQUENCE (READ): Reading the AT25512 via the SO pin requires the following sequence. After the CS line is pulled low to select a device, the Read op-code is transmitted via the SI line followed by the byte address to be read (see Table 3-6 on page 9). Upon completion, any data on the SI line will be ignored. The data (D7 - D0) at the specified address is then shifted out onto the SO line. If only one byte is to be read, the CS line should be driven high after the data comes out. The read sequence can be continued since the byte address is automatically incremented and data will continue to be shifted out. When the highest address is reached, the address counter will roll over to the lowest address allowing the entire memory to be read in one continuous read cycle. WRITE SEQUENCE (WRITE): In order to program the AT25512, two separate instructions must be executed. First, the device must be write enabled via the Write Enable (WREN) Instruction. Then a Write instruction may be executed. Also, the address of the memory location(s) to be programmed must be outside the protected address field location selected by the Block Write 8
AT25512
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AT25512
Protection Level. During an internal write cycle, all commands will be ignored except the RDSR instruction. A Write Instruction requires the following sequence. After the CS line is pulled low to select the device, the Write op-code is transmitted via the SI line followed by the byte address and the data (D7 - D0) to be programmed (see Table 3-6). Programming will start after the CS pin is brought high. (The Low-to-High transition of the CS pin must occur during the SCK low time immediately after clocking in the D0 (LSB) data bit. The Ready/Busy status of the device can be determined by initiating a Read Status Register (RDSR) Instruction. If Bit 0 = 1, the Write cycle is still in progress. If Bit 0 = 0, the Write cycle has ended. Only the Read Status Register instruction is enabled during the Write programming cycle. The AT25512 is capable of a 128-byte Page Write operation. After each byte of data is received, the seven low order address bits are internally incremented by one; the high order bits of the address will remain constant. If more than 128 bytes of data are transmitted, the address counter will roll over and the previously written data will be overwritten. The AT25512 is automatically returned to the write disable state at the completion of a Write cycle. NOTE: If the device is not write enabled (WREN), the device will ignore the Write instruction and will return to the standby state, when CS is brought high. A new CS falling edge is required to re-initiate the serial communication. Table 3-6. Address Key
Address AN AT25512 A15 -A0
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5165E-SEEPR-8/08
4. Timing Diagrams (for SPI Mode 0 (0, 0))
Figure 4-1. Synchronous Data Timing
VIH CS VIL tCSS VIH SCK VIL tSU VIH SI VIL tV VOH SO VOL HI-Z tHO tDIS HI-Z VALID IN tH tWH tWL tCSH tCS
Figure 4-2.
WREN Timing
10
AT25512
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AT25512
Figure 4-3. WRDI Timing
Figure 4-4.
RDSR Timing
CS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCK
SI
INSTRUCTION
SO
HIGH IMPEDANCE
DATA OUT
7 6 5 4 3 2 1 0
MSB
Figure 4-5.
WRSR Timing
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Figure 4-6.
READ Timing
Figure 4-7.
WRITE Timing
Figure 4-8.
CS
HOLD Timing
tCD
tCD
SCK
tHD
HOLD
tHZ
tHD
SO
tLZ
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AT25512
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AT25512
5. Part Marking Scheme
TOP MARK Pin 1 Indicator (Dot) | |---|---|---|---| * H YWW |---|---|---|---|---| 5F 1 |---|---|---|---|---|
BOTTOM MARK |---|---|---|---|---|---|---| PH |---|---|---|---|---|---|---| AAAAAAA |---|---|---|---|---|---|---| <- Pin 1 Indicator
Y = SEAL YEAR WW = SEAL WEEK 6: 2006 0: 2010 02 = Week 2 7: 2007 1: 2011 04 = Week 4 8: 2008 2: 2012 :: : :::: : 9: 2009 3: 2013 :: : :::: :: 50 = Week 50
52 = Week 52
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AT25512N-SH-B/T
Seal Year TOP MARK | Seal Week ||| |---|---|---|---|---|---|---|---| A T ML H YWW |---|---|---|---|---|---|---|---| 5F 1 |---|---|---|---|---|---|---|---| * Lot Number |---|---|---|---|---|---|---|---| | Pin 1 Indicator (Dot) Y = SEAL YEAR WW = SEAL WEEK 6: 2006 0: 2010 02 = Week 2 7: 2007 1: 2011 04 = Week 4 8: 2008 2: 2012 :: : :::: : 9: 2009 3: 2013 :: : :::: :: 50 = Week 50 52 = Week 52
Lot Number to Use ALL Characters in Marking
BOTTOM MARK No Bottom Mark
14
AT25512
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AT25512
AT25512Y7-YH-T
Seal Year TOP MARK | Seal Week ||| |---|---|---|---|---|---|---|---| A TM L HY WW |---|---|---|---|---|---|---|---| 5F 1 |---|---|---|---|---|---|---|---| * Lot Number |---|---|---|---|---|---|---|---| | Pin 1 Indicator (Dot) Y = SEAL YEAR WW = SEAL WEEK 6: 2006 0: 2010 02 = Week 2 7: 2007 1: 2011 04 = Week 4 8: 2008 2: 2012 :: : :::: : 9: 2009 3: 2013 :: : :::: :: 50 = Week 50 52 = Week 52
Lot Number to Use ALL Characters in Marking
BOTTOM MARK No Bottom Mark
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5165E-SEEPR-8/08
6. AT25512 Ordering Information
Ordering Code AT25512N-SH-B AT25512N-SH-T(2) AT25512-TH-B(1) AT25512-TH-T(2) AT25512Y7-YH-T(2) AT25512-W-11(3)
(1)
Voltage 1.8 1.8 1.8 1.8 1.8 1.8
Package 8S1 8S1 8A2 8A2 8Y7 Die Sale
Operation Range Lead-free/Halogen-free NiPDAu Lead Finish Industrial Temperature (-40 C to 85 C) Industrial Temperature (-40 C to 85 C)
Notes:
1. "-B" denotes bulk. 2. "-T" denotes tape and reel. SOIC = 4K per reel. TSSOP = 5K per reel. SAP = 3K per reel. 3. Available in waffle pack, tape and reel, and wafer form; order as SL788 for inkless wafer form. Bumped die available upon request. Please contact Serial Interface Marketing.
Package Type 8S1 8A2 8Y7 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP) 8-lead, 6.00mm x 4.90mm Body, Ultra Thin, Dual Footprint, Non-leaded, Small Array Package (SAP) Options -1.8 Low-voltage (1.8V to 5.5V)
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AT25512
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AT25512
7. Packaging Information 8S1 - JEDEC SOIC
C
1
E
E1
N
L
O
TOP VIEW END VIEW
e b A A1
SYMBOL A A1 b C COMMON DIMENSIONS (Unit of Measure = mm) MIN 1.35 0.10 0.31 0.17 4.80 3.81 5.79 NOM - - - - - - - 1.27 BSC 0.40 0 - - 1.27 8 MAX 1.75 0.25 0.51 0.25 5.05 3.99 6.20 NOTE
D
D E1
SIDE VIEW
E e L
Note: These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.
3/17/05 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TITLE 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC) DRAWING NO. 8S1 REV. C
R
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5165E-SEEPR-8/08
8A2 - TSSOP
3 21
Pin 1 indicator this corner
E1
E
L1
N L
Top View
End View
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN 2.90 NOM 3.00 6.40 BSC 4.30 - 0.80 0.19 4.40 - 1.00 - 0.65 BSC 0.45 0.60 1.00 REF 0.75 4.50 1.20 1.05 0.30 4 3, 5 MAX 3.10 NOTE 2, 5
b
A
D E E1 A
e D
A2
A2 b e
Side View
L L1
Notes:
1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances, datums, etc. 2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed 0.15 mm (0.006 in) per side. 3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm (0.010 in) per side. 4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between protrusion and adjacent lead is 0.07 mm. 5. Dimension D and E1 to be determined at Datum Plane H. 5/30/02
R
2325 Orchard Parkway San Jose, CA 95131
TITLE 8A2, 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)
DRAWING NO. 8A2
REV. B
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AT25512
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AT25512
8Y7 - SAP
PIN 1 INDEX AREA
A
PIN 1 ID
D E1
D1
L
E A
A1
b
e e1
COMMON DIMENSIONS (Unit of Measure = mm)
SYMBOL
MIN - 0.00 5.80 4.70 3.30 3.90 0.35
NOM - - 6.00 4.90 3.40 4.00 0.40 1.27 TYP 3.81 REF
MAX 0.60 0.05 6.20 5.10 3.50 4.10 0.45
NOTE
A A1 D E D1 E1 b e e1 L
0.50
0.60
0.70
10/13/05 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TITLE 8Y7, 8-lead (6.00 x 4.90 mm Body) Ultra-Thin SOIC Array Package (UTSAP) Y7 DRAWING NO. 8Y7 REV. B
R
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5165E-SEEPR-8/08
8. Revision History
Doc. Rev. 5165E 5165D 5165C Date 8/2008 5/2008 8/2007 Comments Updated for 1.8V - 5.5V operation Added part marking diagram information Changed address bit number to seven on page 9 Removed Preliminary status Changed spacing on table notes Reworked figure 4-8 Updated to new template Changed status to Preliminary Initial document release.
5165B
6/2007
5165A
1/2007
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AT25512
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Headquarters
Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600
International
Atmel Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581
Product Contact
Web Site www.atmel.com Technical Support s_eeprom@atmel.com Sales Contact www.atmel.com/contacts
Literature Requests www.atmel.com/literature
Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL'S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL'S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel's products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life.
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5165E-SEEPR-8/08

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